Self-timed design in GaAs - case study of a high-speed parallel multiplier

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Publication Type Journal Article
School or College College of Engineering
Department Computing, School of
Creator Brunvand, Erik L.; Smith, Kent F.
Other Author Chandramouli, V.
Title Self-timed design in GaAs - case study of a high-speed parallel multiplier
Date 1996
Description Abstract-The problems with synchronous designs at high clock frequencies have been well documented. This makes an asynchronous approach attractive for high speed technologies like GaAs. We investigate the issues involved by describing the design of a parallel multiplier that can be part of a floating point multiplier. We first present a new architecture called the partial army of array (PAA) that is more regular than a partial tree approach while having the same latency. We then show how this architecture can be used in a self-timed implementation in the style of micropipelines. We next describe how we can design the final carry propagate adder using a new precharged logic family in GaAs that we developed as part of this project. We conclude with some genera1 observations on doing asynchronous design in GaAs.
Type Text
Publisher Institute of Electrical and Electronics Engineers (IEEE)
Volume 4
Issue 1
First Page 146
Last Page 149
Language eng
Bibliographic Citation Chandramouli, V., Brunvand, E. L., & Smith, K. F. (1996). Self-timed design in GaAs - case study of a high-speed parallel multiplier. IEEE Transactions on VLSI Systems, 4(1), 146-9. March.
Rights Management (c) 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Format Medium application/pdf
Format Extent 685,738 bytes
Identifier ir-main,15753
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Reference URL https://collections.lib.utah.edu/ark:/87278/s6nz8rx9
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