C-RISC A C language reduced instruction set computer

This project is the implementation of a Reduced Instruction Set Computer (RISC) on a tiny chip. RISC technology is based on the idea that a small number of simple instructions can be used to create a fast, flexible computer. Our RISC uses this principle while staying within the confines of the tiny chip. Size limitations directly affect the complexity in the number of possible instructions. Since the tiny chip is limited in size, a decision was required as to the set of instructions to include. Due to the implementers' knowledge of the C language, it was decided that the direction of the RISC instructions would follow the C language instruction set, hence the name C-RISC. The decision to direct the instruction set to the C language instructions does not restrict the flexibility of the C-RISC since many high level languages (HLLs) can be converted or cross-compiled into C code. The adoption of a given language direction allows easier comparison of quantitative results when deciding on instructions to be included in or discarded from the instruction set. A number of ingenious ideas were incorporated into the design of the C-RISC. These were necessitated by the small chip size as well as the desired power of the processor. The final C-RISC chip was implemented in Path Programmable Logic (PPL) [1] using 2 micron CMOS technology.