The 'test model-checking' approach to the verification of formal memory models of multiprocessors

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Publication Type technical report
School or College College of Engineering
Department Computing, School of
Program Advanced Research Projects Agency
Creator Gopalakrishnan, Ganesh
Other Author Nalumansu, Ratan; Ghughal, Rajnish; Mokkedem, Abdel
Title The 'test model-checking' approach to the verification of formal memory models of multiprocessors
Date 1998
Description We offer a solution to the problem of verifying formal memory models of processors by com bining the strengths of model checking and a formal testing procedure for parallel machines We characterize the formal basis for abstracting the tests into test automata and associated memory rule safety properties whose violations pinpoint the ordering rule being violated Our experimen tal results on Verilog models of a commercial split transaction bus demonstrates the ability of our method to e??ectively debug design models during early stages of their development
Type Text
Publisher University of Utah
Subject Formal memory models; Shared memory multiprocessors; Formal testing; Model; Checking
Subject LCSH Multiprocessors
Language eng
Bibliographic Citation Nalumansu, R., Ghughal, R., Mokkedem, A., & Gopalakrishnan, G. (1998). The 'test model-checking' approach to the verification of formal memory models of multiprocessors. UUCS-98-008.
Series University of Utah Computer Science Technical Report
Relation is Part of ARPANET
Rights Management ©University of Utah
Format Medium application/pdf
Format Extent 301,275 bytes
Source University of Utah School of Computing
ARK ark:/87278/s68d0dj8
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2015-04-24
ID 703982
Reference URL https://collections.lib.utah.edu/ark:/87278/s68d0dj8
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