Automatic abstraction for synthesis and verification of deterministic timed systems

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Publication Type Journal Article
School or College College of Engineering
Department Electrical & Computer Engineering
Creator Myers, Chris J.
Other Author Zheng, Hao
Title Automatic abstraction for synthesis and verification of deterministic timed systems
Date 2000
Description This paper presents a new approach for synthesis and verification of asynchronous circuits by using abstraction. It attacks the state explosion problem by avoiding the generation of a flat state space for the whole design. Instead, it breaks the design into sub-blocks and conducts synthesis and verification on each of them. Using this approach, the speed of synthesis and verification improves dramatically. This paper introduces how abstraction is applied to times Petri-nets to speed up synthesis and verification.
Type Text
Publisher Institute of Electrical and Electronics Engineers (IEEE)
Language eng
Bibliographic Citation Zheng, H., & Myers, C. (2000). Automatic abstraction for synthesis and verification of deterministic timed systems. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems. December
Rights Management (c) 2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Format Medium application/pdf
Format Extent 264,522 bytes
Identifier ir-main,15036
ARK ark:/87278/s61269w5
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2021-05-06
ID 703748
Reference URL https://collections.lib.utah.edu/ark:/87278/s61269w5
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