Efficient symbolic simulation based verification using the parametric form of boolean expressions (rev.)

We present several new techniques to make symbolic simulation based verification efficient. These techniques hinge on the use of the parametric form of a boolean expression (e.g. the parametric form for the boolean expression XQ V -<xi is the equivalent expression 3a b . (XQ = a V 6) A (xi = b), where a and b are the parameters). We illustrate several uses of the parametric form that reduce the number of symbolic simulation vectors as well as the time for symbolic simulation based verification. In the first technique, applicable to the verification of non-regular designs, minimally instantiated symbolic simulation vectors are first generated, and all these vectors are encoded into one vector using parametric variables. The second technique also pertains to non-regular designs, and offers a way to compactly encode input constraints using the parametric form during symbolic simulation. The third technique relates to the verification of regular arrays. It is shown that many regular arrays require input constraints to be obeyed, and that these constraints can be encoded using parametric variables. Experimental results are obtained using the COSMOS symbolic simulator, and are used to compare the relative merits of the various techniques. In all the examples considered, the use of the parametric form enhances the speed of the symbolic simulation process, mainly through a favorable tradeoff between the number of simulation vectors (which are very much reduced) and the average number of symbolic variables per vector (which go up only by a small amount).