Timed event/level structures

This paper presents timed event/level(TEL) structures, an extension to timed event-rule structures, which allows the general use of signal levels and timing in the specification of an asynchronous circuit. TEL structures can express true OR causality, as well as language constructs that are very difficult to describe using purely event based specification methods. This flexibility makes it possible to easily express VHDL and CSP handshaking specifications as TEL structures. Circuits can be synthesized from timed event/level structures using a modified version of the geometric timing analysis method without any significant increase in synthesis time. Therefore, timed event/level structures increase specification flexiblity without impacting synthesis performance.