A transformational approach to asynchronous high-level synthesis

Asynchronous high-level synthesis is aimed at transforming high level descriptions of algorithms into efficient asynchronous circuit implementations. This approach is attractive from the point of view of the flexibility it affords in performing high level program transformations on users' initial descriptions, the faithfulness with which it supports the communicating process model of computation, and the ease with which it accommodates computations that have data dependent control-flow decisions as well as data dependent execution times. In this paper, we take the reader through the entire process of synthesizing two asynchronous circuits using our high level synthesis tool, SHILPA, starting from input descriptions in hopCP, emphasizing the program transformation techniques employed in the process. Specifically, we show how tail-recursive loops with accumulating parameters can be software pipelined, by evaluating the accumulating parameters in separate processes. We then show how the resulting hopCP flow graphs (HFGs) are transformed through action refinement resulting in normal form HFGs (NHFGs). NHFGs are then technology mapped onto an Actel FPGA implementation. Our results are illustrated on a pipelined factorial circuit and a pipelined integer square-root circuit.