An optimal, parallel discrete relaxation algorithm and architecture (Revised January 1988 and August 1989)

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Publication Type technical report
School or College College of Engineering
Department Computing, School of
Creator Gu, Jun
Title An optimal, parallel discrete relaxation algorithm and architecture (Revised January 1988 and August 1989)
Date 1988
Description A variety of problems in artificial intelligence, operations research, symbolic logic, pattern recognition and computer vision, and robot manipulation are special cases of the Consistent Labeling Problem (CLP). The Discrete Relaxation Algorithm (DRA) is an efficient computational technique to enforce arc consistency (AC) in a CLP problem. The original sequential AC-1 algorithm suffers from 0 ( n 3m3 ) time complexity, for an n-object and mlabel problem. Sample problem runs show all these algorithms are too slow to meet the need for any useful real-time CLP applications. In this paper, we give an optimal, parallel DRA5 algorithm which reaches the optimal lower bound, O(nm), for parallel AC algorithms (where the number of processors is polynomial in the problem size). This algorithm has been implemented on a fine-grained, massively parallel hardware computer architecture. For problems of practical interest, four to ten orders of magnitude of efficiency improvement can be reached on this hardware architecture.
Type Text
Publisher University of Utah
First Page 1
Last Page 37
Subject Consistent Labeling Problem; CLP; Discrete Relaxation Algorithm; DRA
Subject LCSH Parallel algorithms
Language eng
Bibliographic Citation Gu, J. (1988). An optimal, parallel discrete relaxation algorithm and architecture. 1-37. UUCS-TR-88-006.
Series University of Utah Computer Science Technical Report
Relation is Part of ARPANET
Rights Management ©University of Utah
Format Medium application/pdf
Format Extent 6,033,913 bytes
Identifier ir-main,16144
ARK ark:/87278/s6sx6x9f
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2015-04-22
ID 702332
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