An optimal, parallel discrete relaxation algorithm and architecture (Revised January 1988 and August 1989)

A variety of problems in artificial intelligence, operations research, symbolic logic, pattern recognition and computer vision, and robot manipulation are special cases of the Consistent Labeling Problem (CLP). The Discrete Relaxation Algorithm (DRA) is an efficient computational technique to enforce arc consistency (AC) in a CLP problem. The original sequential AC-1 algorithm suffers from 0 ( n 3m3 ) time complexity, for an n-object and mlabel problem. Sample problem runs show all these algorithms are too slow to meet the need for any useful real-time CLP applications. In this paper, we give an optimal, parallel DRA5 algorithm which reaches the optimal lower bound, O(nm), for parallel AC algorithms (where the number of processors is polynomial in the problem size). This algorithm has been implemented on a fine-grained, massively parallel hardware computer architecture. For problems of practical interest, four to ten orders of magnitude of efficiency improvement can be reached on this hardware architecture.