Algorithms for MIS vector generation and pruning

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Publication Type Journal Article
School or College College of Engineering
Department Electrical & Computer Engineering
Creator Stevens, Kenneth
Other Author Dartu, Florentin
Title Algorithms for MIS vector generation and pruning
Date 2006
Description Ignoring the effect of simultaneous switching for logic gates causes silicon failures for high performance microprocessor designs. The main reason to omit this effect is the run time penalty and potential over-conservatism. Run times are directly proportional to the vector sizes. Efficient algorithms are presented that prune the multiple input switching (MIS) vector set to a worst-case covering using a boolean logic abstraction of the gate. This non-physical representation reduces the vector size to approximately n vectors for an n-input gate. This is effectively the same vector set size as the optimal single input switching vector set. There are no errors for 88% the simulations using a Monty-Carlo coverage on a 90nm static library, and the magnitude of the errors are less than 5% on average.
Type Text
Publisher Institute of Electrical and Electronics Engineers (IEEE)
First Page 408
Last Page 414
Language eng
Bibliographic Citation Stevens, K. S., & Dartu, F. (2006). Algorithms for MIS vector generation and pruning. Proceedings of the International Conference on Computer-Aided Design (ICCAD-06), 408-14.
Rights Management (c) 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Format Medium application/pdf
Format Extent 8,740,386 bytes
Identifier ir-main,15285
ARK ark:/87278/s6891pxv
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2021-05-06
ID 702283
Reference URL https://collections.lib.utah.edu/ark:/87278/s6891pxv
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