Design and optimization of asynchronous network-on-chip

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Publication Type dissertation
School or College College of Engineering
Department Electrical & Computer Engineering
Author You, Junbok
Title Design and optimization of asynchronous network-on-chip
Date 2011-12
Description The bandwidth requirement for each link on a network-on-chip (NoC) may differ based on topology and traffic properties of the IP cores. Available bandwidth on an asynchronous NoC link will also vary depending on the wire length between sender and receiver. This work explores the benefit to NoC performance, area, and energy when this property is used to optimize bandwidth on specific links based on its bandwidth required by a target SoC design. Three asynchronous routers were designed for implementing of asynchronous NoCs. Simple routing scheme and single-flit packet format lead to performance- and area-efficient router designs. Their performance was evaluated in consideration of link wire delay. Comprehensive analysis of pipeline latch insertion in asynchronous communication links is performed in regard to link bandwidth. Optimal placement of pipeline latch for maximizing benefit to increase of bandwidth is described. Specific methods are proposed for performance, area and energy optimization, respectively. Performance optimization is achieved by increasing bandwidth of high trafficked and high utilized links in an NoC, as inserting pipeline latches in those links. Through decrease of bandwidth of links with low traffic and low utilization by halving data-path width, reduction of wire area of an NoC is accomplished. Energy optimization is performed using wide spacing between wires in links with high energy consumption. An analytical model for asynchronous link bandwidth estimation is presented. It is utilized to deploy NoC optimization methods as identifying adequate links for each optimization method. Energy and latency characteristics of an asynchronous NoC are compared to a similarly-designed synchronous NoC. The results indicate that the asynchronous network has lower energy, and link-specific bandwidth optimization has improved NoC performance. Evaluation of proposed optimization methods by employing to an asynchronous NoC shows achievements of performance enhancement, wire area reduction and wire energy saving.
Type Text
Publisher University of Utah
Subject Asynchronous circuit design; Digital VLSI design; Interconnect system; Network-on-chip; System-on-chip
Dissertation Institution University of Utah
Dissertation Name Doctor of Philosophy
Language eng
Rights Management Copyright © Junbok You 2011
Format Medium application/pdf
Format Extent 915,446 bytes
Identifier us-etd3,74146
Source Original in Marriott LIbrary Special Collections, TK7.5 2011 .Y68
ARK ark:/87278/s6n59245
Setname ir_etd
Date Created 2012-04-24
Date Modified 2018-04-26
ID 194738
Reference URL https://collections.lib.utah.edu/ark:/87278/s6n59245