Automatic extraction of behavioral models from simulations of analog/mixed-signal (AMS) circuits

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Publication Type thesis
School or College College of Engineering
Department Electrical & Computer Engineering
Author Batchu, Satish
Title Automatic extraction of behavioral models from simulations of analog/mixed-signal (AMS) circuits
Date 2011-05
Description Verification of analog circuits is becoming a bottle-neck for the verification of complex analog/mixed-signal (AMS) circuits. In order to assist functional verification of complex AMS system-on-chips (SoCs), there is a need to represent the transistor-level circuits in the form of abstract models. The ability to represent the analog circuits as behavioral models is necessary, but not sufficient. Though there exist languages like Verilog-AMS and VHDL-AMS for modeling AMS circuits, there is no easy method for generating these models directly from the transistor-level descriptions. This thesis presents an improved method for extracting behavioral models from the simulations of AMS circuits. This method generates labeled Petri net (LPN) models that can be used in the formal verification of circuits, and SystemVerilog models that can be used in the system-level simulations.
Type Text
Publisher University of Utah
Subject AMS; Analog/mixed-signal; Modeling; Petri-net; Simulation; Verification
Dissertation Institution University of Utah
Dissertation Name Master of Science
Language eng
Rights Management Copyright © Satish Batchu 2011
Format Medium application/pdf
Format Extent 916,315 bytes
Identifier us-etd3,13616
Source Original in Marriott LIbrary Special Collections, TK7.5 2011 .B38
ARK ark:/87278/s6wd4f9n
Setname ir_etd
Date Created 2012-04-24
Date Modified 2017-05-11
ID 194593
Reference URL https://collections.lib.utah.edu/ark:/87278/s6wd4f9n
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