Low power PLL building blocks

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Publication Type dissertation
School or College College of Engineering
Department Electrical & Computer Engineering
Author Kier, Ryan J
Title Low power PLL building blocks
Date 2010-08
Description In recent years integrated circuit power consumption has become one of the most important and critical performance specifications for a wide range of mobile, battery-operated devices. This dissertation addresses the significant power dissipation limitations imposed on a fully implantable wireless neural recording system in which power must be minimized to avoid cellular necrosis. Two core PLL circuits, the voltage-controlled oscillator (VCO) and multimodulus divider, have been developed in a 0.6-?m BiCMOS process technology with a power dissipation target of 4.5 mW with a typical output frequency of 915 MHz. To facilitate the development of a low power VCO, a novel integrated inductor design method is proposed to optimize inductors specifically for power dissipation. Such optimized inductors result in minimum operating currents up to 25 times lower than inductors optimized for Q.
Type Text
Publisher University of Utah
Subject Inductor modeling; Integrated inductor; PLL; TSPC frequency divider; VCO; Wireless neural recording
Subject LCSH Implants, Artificial; Implants, Artificial -- Biocompatibility
Dissertation Institution University of Utah
Dissertation Name PhD
Language eng
Rights Management ©Ryan J. Kier
Format Medium application/pdf
Format Extent 5,964,433 bytes
Source Original in Marriott Library Special Collections, RD14.5 2010 .K54
ARK ark:/87278/s6dn4kjh
Setname ir_etd
Date Created 2012-04-23
Date Modified 2017-09-26
ID 192368
Reference URL https://collections.lib.utah.edu/ark:/87278/s6dn4kjh