{"responseHeader":{"status":0,"QTime":4,"params":{"q":"{!q.op=AND}id:\"106689\"","hl":"true","hl.simple.post":"","hl.fragsize":"5000","fq":"!embargo_tdt:[NOW TO *]","hl.fl":"ocr_t","hl.method":"unified","wt":"json","hl.simple.pre":""}},"response":{"numFound":1,"start":0,"docs":[{"modified_tdt":"2016-11-18T00:00:00Z","thumb_s":"/80/58/80587b0b1c524ef004cb45d5218c191f658e97ae.jpg","oldid_t":"compsci 14802","setname_s":"ir_computersa","file_s":"/99/a7/99a7fd1a87a92531570dd6bba1e7e8b2b576a92e.pdf","title_t":"Page 18","ocr_t":"currently limited to a small number of gates (approximately 5000). PLAs [2, 32, 42, 48, 54, 80, 81J have ree1ved much attention. ManY of these PLA generating softWare systems know how to compile synchronous control-units and boolean expressions from some higher level description. The FLA is widely used in integrated circuits for control and random logic. Other attempts being made at inventive cirouit design include HacroCells [5], General Logic CirCuits (CiLe) [62J, Associative Logic [24, 25], Programmable Array Logic (PAL) [19] and Enhanced Programmable Logic Arrays [15]. - . - The University of Utah has been involved for the past three years in implementing a derivative of the PLA. It has been- mown in the past as the SLA and is currently known as Path-Programmable Logic (PPL). PP-L, like the SLA, is a circuit implementation technique where logic and connection cells are placed in a rectangular array where the rows' and columns act respectively as the AND and OR planes of the PLA. The SLA was originally proposed by Patil [59, 60] and has' been studied in 12L [46, 69], NMOS [10], and in CMOS [1, 8, 9, 11 J. Tbe SLA (PFL) offers a substantial improvement over other circuit implementation teohniques, especially in the area of CAD tool development [72]. The r:.exible and regular structure of PFL programs allow for development of sophisticated software systems composing integrated circuits from high level descriptions using PPL as an implementation methodology. ;[nile the ostensible purpose of this thesis is to prove that speed-independept control-units can be automatically implemented in","restricted_i":0,"id":106689,"created_tdt":"2016-11-18T00:00:00Z","format_t":"application/pdf","parent_i":106839,"_version_":1642982438717095937}]},"highlighting":{"106689":{"ocr_t":[]}}}