{"responseHeader":{"status":0,"QTime":2,"params":{"q":"{!q.op=AND}id:\"100420\"","hl":"true","hl.simple.post":"","hl.fragsize":"5000","fq":"!embargo_tdt:[NOW TO *]","hl.fl":"ocr_t","hl.method":"unified","wt":"json","hl.simple.pre":""}},"response":{"numFound":1,"start":0,"docs":[{"file_name_t":"Neff-Instead_An_Integrated.pdf","thumb_s":"/20/72/20727f54b5b8bff3aa3c6594819d1f1aa34d50b5.jpg","oldid_t":"compsci 8533","setname_s":"ir_computersa","restricted_i":0,"format_t":"application/pdf","modified_tdt":"2016-05-25T00:00:00Z","file_s":"/4c/b7/4cb7f539e2f4851a83e414a6948b00984b0316d6.pdf","title_t":"Page 83","ocr_t":"75 • Use hierarchy to reduce the total number of tiles and ports. There is at least one bright spot in all this storage inefficiency gloom. In circuits like the ATQ, where most of the tiles are unit-sized, and all of them covering their origin, it seems, at first glance, quite wasteful for INSTED to store a list containing one tile at each grid location so covered, especially since storing lists normally takes twice as many words as the number of elements they contain. Fortunately, however, the Symbolics allows lists to be \"cdr-coded\" and thereby stored in half the space, or just one word per list element. 5.1.3 Network Extraction Ports must also shoulder the blame (but not entirely, as the analysis below shows) for the incredibly slow operations whereby a network is extracted for simulation, profiled for ATQ in Table 4. One and a half hours to do depth-first tracing of network connectivity is, quite simply, intolerable. Subtracting the half-hour consumed in paging still leaves sixty long minutes, which is hardly better .. The :TRACE port method is a major exception to functions exhibiting linear growth rate behavior. Consulting [17], this can be shown to have quadratic (0(N2)) running time in the worst case, as per the following argument: The bulk of the body of the :TRACE method is the :VISIT-AND-TAG port method it calls. Since this is executed exactly once for each port instance, one would expect the time complexity to be linear in the number of ports. However, the time consumed in the :VISIT-AND-TAG method is not constant, thanks to the step of updating of the global *NODE-POR.TS-ALIST* variable, which keeps track of the ports that are associated with each node. Instead, in the worst case, this list must be walked completely before a new node name is appended to it. This means that the growth rate is itself increasing at a linear rate, making the whole algorithm quadratic. In other words, the time complexity is proportional to the sum of the simple arithmetic sequence (1 + 2 + 3 + ... + N) which equals (N*(N+1))/2 which is OCN2). N here is actually the total number of nodes, which is much less than the number of ports. Still, this is much too slow for real circuits, which may have several thousand nodes. (ATQ has over 9,000 nodes.)","id":100420,"created_tdt":"2016-05-25T00:00:00Z","parent_i":100459,"_version_":1679953650277941248}]},"highlighting":{"100420":{"ocr_t":[]}}}