Publication Type |
Journal Article |
Department |
Computing, School of |
Creator |
Sudan, Kshitij |
Other Author |
Awasthi, Manu; Shevgoor, Manjunath; Rajendran, Bipin; Balasubramonian, Rajeev; Srinivasan, Viji |
Title |
Efficient scrub mechanisms for error-prone emerging memories |
Date |
2012-01-01 |
Description |
Many memory cell technologies are being considered as possible replacements for DRAM and Flash technologies, both of which are nearing their scaling limits. While these new cells (PCM, STT-RAM, FeRAM, etc.) promise high density, better scaling, and non-volatility, they introduce new challenges. Solutions at the architecture level can help address some of these problems; e.g., prior re-search has proposed wear-leveling and hard error tolerance mechanisms to overcome the limited write endurance of PCM cells. In this paper, we focus on the soft error problem in PCM, a topic that has received little attention in the architecture community. Soft errors in DRAM memories are typically addressed by having SECDED support and a scrub mechanism. The scrub mechanism scans the memory looking for a single-bit error and corrects it be-fore the line experiences a second uncorrectable error. However, PCM (and other emerging memories) are prone to new sources of soft errors. In particular, multi-level cell (MLC) PCM devices will suffer from resistance drift, that increases the soft error rate and incurs high overheads for the scrub mechanism. This paper is the first to study the design of architectural scrub mechanisms, especially when tailored to the drift phenomenon in MLC PCM. Many of our solutions will also apply to other soft-error prone emerging memories. We first show that scrub overheads can be reduced with support for strong ECC codes and a lightweight error detection operation. We then design different scrub algorithms that can adaptively trade-off soft and hard errors. Using an approach that combines all proposed solutions, our scrub mechanism yields a 96.5% reduction in uncorrectable errors, a 24.4 × decrease in scrub-related writes, and a 37.8% reduction in scrub energy, relative to a basic scrub algorithm used in modern DRAM systems. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
Volume |
6168914 |
First Page |
15 |
Last Page |
26 |
Dissertation Institution |
University of Utah |
Language |
eng |
Bibliographic Citation |
Awasthi, M., Shevgoor, M., Sudan, K., Rajendran, B., Balasubramonian, R., & Srinivasan, V. (2012). Efficient scrub mechanisms for error-prone emerging memories. Proceedings - International Symposium on High-Performance Computer Architecture, 6168941, 15-26. |
Rights Management |
(c) 2012 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
Format Medium |
application/pdf |
Format Extent |
440,540 bytes |
Identifier |
uspace,17312 |
ARK |
ark:/87278/s6db8kn8 |
Setname |
ir_uspace |
ID |
707942 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6db8kn8 |